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_______________ge ne ra l de sc ript ion maxims dg528/dg529 are monolithic, 8-channel, cmos multiplexers with on-board address and control latches that simplify design and reduce board space in microprocessor-based applications. the dg528 is a single-ended, 1-of-8 multiplexer, while the dg529 i s a differential, 2-of-8 multiplexer. these devices can oper- ate as multiplexers or demultiplexers. the dg528/dg529 have break-before-make switching to prevent momentary shorting of the input signals. each device operates with dual supplies (4.5v to 20v) or a single supply (+5v to +30v). all logic i nputs are ttl and cmos compatible. the maxim dg528/dg529 are pin and electrically compatible wit h the industry-standard dg528/dg529. ________________________applic a t ions data-acquisition systems automatic test equipment avionics and military systems communication systems microprocessor-controlled systems audio-signal multiplexing ____________________________fe a t ure s ? low-power, monolithic cmos design ? on-board address latches ? break-before-make input switches ? ttl and cmos logic compatible ? microprocessor-bus compatible ? r ds(on) < 400 ? pin and electrically compatible with the industry-standard dg528/dg529 and adg528/adg529 dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs ________________________________________________________________ maxim integrated products 1 _________________pin configura t ions __________typic a l ope ra t ing circ uit ca ll t oll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 for fre e sa m ple s or lit e ra t ure . 19-3519; rev 0; 3/91 part dg528 cj dg528cwn dg528ck 0c to +70c 0c to +70c 0c to +70c temp. range pin-package 18 plastic dip 18 wide so 18 cerdip ______________orde ring i nform a t ion ordering information continued at end of data sheet. * contact factory for dice specifications. ** contact factory for availability and processing to mil-std-883. dg528c/d dg528dj -40c to +85c 0c to +70c dice* 18 plastic dip dg528dn -40c to +85c 20 plcc dg528ewn -40c to +85c 18 wide so dg528dk -40c to +85c 18 cerdip dg528az -55c to +125c 20 lcc** dg528ak -55c to +125c 18 cerdip** dg529 max133 wr rs +5v -5v mux and a/d control a0 a1 in1a m p interface in1b in2a in2b in3a outa outb in3b in4a in4b differential input for data-acquisition systems 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 rs a1 a2 gnd v+ s5 s6 s7 s8 wr a0 en v- s1 s2 s3 s4 d top view 10 9 dip/so dg528 pin configurations continued at end of data sheet. downloaded from: http:///
dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = 15v, v- = -15v, v en = 2.4v, wr = 0v, rs = 2.4v, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended per iods may affect device reliability. voltage referenced to v- v+ ................................................. ...................................+44v gnd ................................................ .................................+25v digital inputs v s , v d ................................................. v- -2v to v+ +2v or 20ma, whichever occurs first. current (any terminal, except s or d) .............. ...................30ma continuous current, s or d peak current, s or d ............................... ............................20ma (pulsed at 1ms, 10% duty cycle max) ................ ............50ma continuous power dissipation (t a = +70c) (note 1) 18-pin plastic dip (derate 11.11mw/c above +70c). ..889mw 18-pin wide so (derate 9.52mw/c above +70c) ....76 2mw 18-pin cerdip (derate 10.53mw/c above +70c)....84 2mw 20-pin plcc (derate 10.00mw/c above +70c) .......8 00mw 20-pin lcc (derate 9.09mw/c above +70c) .......... .727mw operating temperature ranges dg52_c_ ............................................ ................0c to +70c dg52_d_/e_ ......................................... ...........-40c to +85c dg52_a_ ............................................ ...........-55c to +125c storage temperature range .......................... ...-65c to +150c lead temperature (soldering, 10sec) ................ .............+300c v d = 10v, v al = 0.8v, i s = -200a, v ah = 2.4 (note 3) v en = 0v, v s = 10v, v d = 10v v ah = 2.4v, v s = v d = 10v, v al = 0.8v, v en = 2.4v -10v < v s < 10v v en = 0v, v s = 10v, v d = 10v conditions -30 -0.01 i al address input current, input voltage low a -1 -0.002 1 30 i ah address input current, input voltage high -1 -0.006 1 -30 a -1 -0.002 1 na -100 -0.015 100 i d(on) drain-on leakage current (notes 3, 4) -10 -0.015 10 -200 -0.03 200 -10 -0.03 10 270 400 v -15 15 v analog analog-signal range na -100 -0.008 100 i d(off) drain-off leakage current -10 -0.008 10 -200 -0.015 200 -10 -0.015 10 500 r ds(on) drain-source on-resistance % 6 ? r ds(on) greatest change in drain- source on-resistance between channels -1 -0.005 1 na -50 -0.005 50 i s(off) source-off leakage current units dg52_a min typ max symbol v a = rs = wr = 0v, v en = 0v or 2.4v v a = 15v (note 2) dg529 dg529 dg528 dg528 t a = t max t a = +25c, t min t a = +25c t a = t max v a = 2.4v t a = t max t a = +25c t a = t max t a = +25c t a = t max t a = +25c t a = t max t a = +25c t a = +25c t a = t max t a = +25c -30 -0.01 -1 -0.002 1 30 -1 -0.006 1 -30 -1 -0.002 1 -100 -0.015 100 -20 -0.015 20 -200 -0.03 200 -20 -0.03 20 270 450 -15 15 -100 -0.008 100 -20 -0.008 20 -200 -0.015 200 -20 -0.015 20 500 6 -5 -0.005 5 -50 -0.005 50 dg52_c/d/e min typ max t a = t max t a = +25c t a = t max t a = +25c parameter note 1: all leads are soldered or welded to pc board. switch input downloaded from: http:///
dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs _______________________________________________________________________________________ 3 note 2: guaranteed by design. note 3: sequence each switch on. note 4: i d(on) is leakage from driver into on switch. note 5: reset pulse period must be at least 50s during or after power-on. electrical characteristics (v+ = 15v, v- = -15v, v en = 2.4v, wr = 0v, rs = 2.4v, t a = t min to t max , unless otherwise noted.) figure 7 (stabilization time) figure 7 (hold time) figure 7 figure 7; v s = 5v (note 5) 300 15 180 12 30 10 500 150 wr pulse width t ww 300 150 ns ax, en data valid to wr t dw 180 120 ns ax, en data valid after wr t wd 30 10 ns rs pulse width t rs 500 150 ns t a = +25c t a = +25c f = 1mhz t a = +25c t a = +25c t a = +25c t a = +25c t a = +25c t a = +25c t a = +25c t a = +25c t a = +25c t a = +25c v en = 0v, r l = 1k , c l = 15pf, v s = 7v rms , f = 500khz figure 6 figures 3, 5 figures 3, 4 v en = 0v, f = 140khz, v s = 0v dg528 figure 1 figure 2 dg52_c/d/e min typ max 68 4 1.5 1.5 2.5 5 1.5 0.2 25 12 0.003 2.5 -1.5 0.01 parameter symbol dg52_a min typ max units off isolation o irr 68 db charge injection q 4 pc enable, reset turn-off time t off(en, rs ) 0.4 1 s enable, write turn-on time t on(en, wr ) 1.0 1.5 s logic-input capacitance c in 2.5 pf source-off capacitance c s(off) 5 pf switching time of multiplexer t trans 0.4 1 s break-before-make interval t open 0.2 s 25 drain-off capacitance c d(off) 12 pf positive supply current i+ 0.003 2.5 ma negative supply current i- -1.5 0.01 ma conditions v en = 0v, f = 140khz, v s = 0v v en = v ah = 0v v en = v ah = 0v dg529 dynamic supply minimum input timing downloaded from: http:///
dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs 4 _______________________________________________________________________________________ v in1 0 50% +3v 0 0.8v in8 0.8v in1 v in8 dg529 outb in4b switch output in1a to in4a outa, in2b to in3b in1b logic input a1 a0 10v 10v 35pf v ob rs en t transition in8 on logic input t r < 20ns t f < 20ns switch output v o t transition in1 on gnd wr v+ v- -15v +15v +2.4v 50 w 1m dg528 out in8 switch output in2 to in7 in1 logic input a2 a1 a0 10v 10v 35pf v o rs en gnd wr v+ v- -15v +15v +2.4v 50 w 1m figure 1. transition-time test circuits v in 0 0v 50% +3v 80% 0v dg529 outb switch output in_ and outa logic input a0, a1 (a2) 35pf v o rs +5v en t open +1.5v +3v +1.5v logic input t r < 20ns t f < 20ns switch output v o gnd wr v+ v- -15v +15v +2.4v 50 w 1k figure 2. open-time (b.b.m.) interval test circuit downloaded from: http:///
dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs _______________________________________________________________________________________ 5 0.1 v o 0.9 v o v o v in1 0 50% +3v 0 0.1 v o logic input t r < 20ns t f < 20ns switch output v o t on(en) t off(en) dg528 out switch output in2 to in8 in1 logic input a2 a1 a0 -5v 35pf v o en gnd wr v+ v- -15v +15v rs +2.4v 50 w 1k dg529 outb out switch output in1b logic input a1 a0 -5v 35pf v ob en gnd wr v+ v- -15v +15v rs +2.4v 50 w 1k in1a to in4a outa in2b, in3b, in4b figure 3. enable t on /t off time test circuit 0 0 +1.5v +3v dg529 outb out switch output in1 or in1b remaining switches logic input a0, a1 (a2) 35pf v o rs +5v en 50% device must be reset prior to applying wr pulse 0.2 v o wr switch output v o gnd v+ v- -15v +15v +2.4v 1k rs wr wr t on(wr) figure 4. write turn-on time t on(wr) test circuit downloaded from: http:///
dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs 6 _______________________________________________________________________________________ 0 0 +1.5v +3v outb out switch output in1 or in1b remaining switches logic input a0, a1 (a2) * as shown 35pf v o rs +5v en 50% 0.8 v o rs switch output v o gnd v+ v- -15v +15v +2.4v 1k wr t off(rs) dg528* figure 5. reset turn-off time t off(rs) test circuit 0 0 +3v +3v +1.5v +0.8v +2.0v wr en, a0, a1, (a2) t wd t dw t ww 0 v o 0 +3v +1.5v 0.8 v o rs switch output t off(rs) t rs figure 7. typical timing diagrams for dg528/dg529 en v o d v o rs d v gen r gen a0, a1 (a2) cl = 1000pf v o en s_ d v o is the measure of voltage error due to charge injection. the charge injection in coulombs is q = c l x d v o . gnd v+ v- -15v +15v +2.4v wr * as shown dg528* figure 6. charge-injection test circuit downloaded from: http:///
_______________de t a ile d de sc ript ion the internal structures of the dg528/dg529 include translators for the a2/a1/a0/en/wr /rs digital inputs, latches, and a decode section for channel selection (truth tables). the gate structures consist of par allel combinations of n and p mosfets. write (wr ) and reset (rs ) strobes are provided for interfacing with p-bus lines (figure 9), alleviati ng the need for the p to provide constant address inputs to the mux to hold a particular channel. when the wr strobe is in the low state (less than 0.8v) and the rs strobe is in the high state (greater than 2.4v), the muxes are in the transparent modethey a ct similarly to nonlatching devices, such as the dg508 a/ dg509a or the hi508/hi509. when the wr goes high, the previous bcd address input is latched and held in that state indefinitel y. to pull the mux out of this state, either wr must be taken low to the transition state, or rs must be taken low to turn off all channels. rs turns off all channels when it is low, which resets channel selection to the channel 1 mode. the dg528/dg529 work with both single and dual sup- plies and function over the +5v to +30v single-supp ly range. for example, with a single +15v power supply , analog signals in the 0v to +15v range can be switched normally. if negative signals around 0v a re expected, a negative supply is needed. however, onl y -5v is needed to normally switch signals in the -5v to +15v range (-5v, +15v supplies). no current is draw n from the negative supply, so maxims max635 dc-dc converter is an ideal choice. the en latch allows all switches to be turned off u nder program control. this is useful when two or more dg528s are cascaded to build 16-line and larger ana - log-signal multiplexers. dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs _______________________________________________________________________________________ 7 table 1. dg528 logic states table 2. dg529 logic states a2 a1 a0 en wr rs on switch latching x x x x 1 maintains previous switch condition reset x x x x x 0 none (latches cleared) transparent operation x 0 0 0 0 1 1 1 1 x 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 none 1 2 3 4 5 6 7 8 a1 a0 en wr rs on switch x x x 1 maintains previous switch condition x x x x 0 none (latches cleared) x 0 0 1 1 x 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 none 1 2 3 4 latching reset transparent operation note: logic 1: v ah 3 2.4v, logic 0: v al 0.8v. downloaded from: http:///
dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs 8 _______________________________________________________________________________________ protection v- sn s1 d v+ clk reset 4-wide latch rs protection wr protection a_ protection level shift decode en figure 8. simplified internal structure _______________________applic a t ions ope ra t ion w it h supply v olt a ge s ot he r t ha n 1 5 v maxim guarantees the dg528/dg529 for operation from 4.5v to 20v supplies. the switching delays increase by about a factor of two at 5v, and break - before-make action is preserved. the dg528/dg529 can operate with a single +5v to +30v supply as well as asymmetrical power supplies like +15v and -5v. the digital threshold will remai n approximately 1.6v above the gnd pin, and the analo g characteristics such as r ds(on) are determined by the total voltage difference between v+ and v-. connect v- to 0v when operating with a +5v to +30v single supp ly. digit a l i nt e rfa c e le ve ls the typical digital threshold of both the address l ines and en is 1.6v with a temperature coefficient of approximately -3mv/c, ensuring compatibility with ttl logic over the temperature range. the digital thres hold is relatively independent of the power-supply volta ges, going from a typical 1.6v when v+ is 15v to 1.5v ty pi- cal with v+ = 5v. therefore, maxims dg528/dg529 operate with standard ttl logic levels, even with 5v power supplies. in all cases, ens threshold is the same as the other logic inputs and is referenced to gnd. the digital inputs can also be driven with cmos log ic levels swinging from either v+ to v- or from v+ to gnd. the digital input current is just a few nanoamps of leak- age at all input-voltage levels with a guaranteed m axi- mum of 1a. the digital inputs are protected from e sd by a 30v zener diode between the input and v+ and can be driven 2v beyond the supplies without draw- ing excessive current. downloaded from: http:///
dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs _______________________________________________________________________________________ 9 reset wr cs address bus 15v analog inputs 1-of-8 analog inputs v+ +5v -15v +15v v- in1 in2 in3 in4 in5 in6 in7 in8 wr rs en a2 a1 a0 address decoder data bus microprocessor system bus 7432 figure 9. bus interface 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 rs a1 gnd v+ s1b s2b s3b s4b db wr a0 en v- s1a s2a s3a s4a da top view 10 9 dip/so lcc/plcc dg529 14 15 16 17 18 4 5 6 7 8 3 2 1 20 19 9 10 11 12 13 dg528 en v ss s1 s2 s3 a2 gnd v dd s5 s6 a0 wr n.c. rs a1 s4 d n.c. s8 s7 lcc/plcc 14 15 16 17 18 4 5 6 7 8 3 2 1 20 19 9 10 11 12 13 dg529 en v ss s1a s2a s3a gnd v dd s1b s2b s3b a0 wr n.c. rs a1 s4a da n.c. db s4b n.c. = no connect _____________________________________________pin co nfigura t ions (c ont inue d) downloaded from: http:///
dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs 10 ______________________________________________________________________________________ part dg529 cj dg529cwn dg529ck 0c to +70c 0c to +70c 0c to +70c temp. range pin-package 18 plastic dip 18 wide so 18 cerdip dg529c/d dg529dj -40c to +85c 0c to +70c dice* 18 plastic dip dg529dn -40c to +85c 20 plcc dg529ewn -40c to +85c 18 wide so dg529dk -40c to +85c 18 cerdip dg529az -55c to +125c 20 lcc** dg529ak -55c to +125c 18 cerdip** _orde ring i nform a t ion (c ont inue d) * contact factory for dice specifications. ** contact factory for availability and processing to mil-std-883. _________________chip topogra phie s a1 a2 gnd v+ s5 s6 s7 0. 125" (3. 18mm) 0. 131" (3. 33mm) d s8 a0 rs wr en v- s1 s2 s3 s4 a1 gnd v+ s1b s2b s3b s4b 0. 125" (3. 18mm) 0. 131" (3. 33mm) da db a0 rs wr en v- s1a s2a s3a s4a dg528dg529 transistor count: 200 substrate connected to v+ transistor count: 200 substrate connected to v+ downloaded from: http:///
dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs ______________________________________________________________________________________ 11 ___________________________________________________ _____pa c k a ge i nform a t ion dim a a1 a2 a3 b b1 c d1 e e1 e ea eb l min C 0.015 0.125 0.055 0.016 0.045 0.008 0.005 0.300 0.240 0.100 0.300 C 0.115 max 0.200 C 0.175 0.080 0.022 0.065 0.012 0.080 0.325 0.310 C C 0.400 0.150 min C 0.38 3.18 1.40 0.41 1.14 0.20 0.13 7.62 6.10 2.54 7.62 C 2.92 max 5.08 C 4.45 2.03 0.56 1.65 0.30 2.03 8.26 7.87 C C 10.16 3.81 inches millimeters plastic dip plastic dual-in-line package (0.300 in.) dim d d d d d d pkg. p p p p p n min 0.348 0.735 0.745 0.885 1.015 1.14 max 0.390 0.765 0.765 0.915 1.045 1.265 min 8.84 18.67 18.92 22.48 25.78 28.96 max 9.91 19.43 19.43 23.24 26.54 32.13 inches millimeters pins 8 14 16 18 20 24 c a a2 e1 d e ea eb a3 b1 b 0 - 15 a1 l d1 e 21-0043a dim a a1 b c e e h l min 0.093 0.004 0.014 0.009 0.291 0.394 0.016 max 0.104 0.012 0.019 0.013 0.299 0.419 0.050 min 2.35 0.10 0.35 0.23 7.40 10.00 0.40 max 2.65 0.30 0.49 0.32 7.60 10.65 1.27 inches millimeters 21-0042a wide so small-outline package (0.300 in.) dim d d d d d min 0.398 0.447 0.496 0.598 0.697 max 0.413 0.463 0.512 0.614 0.713 min 10.10 11.35 12.60 15.20 17.70 max 10.50 11.75 13.00 15.60 18.10 inches millimeters pins 16 18 20 24 28 1.27 0.050 l h e d e a a1 c 0- 8 0.101mm 0.004in. b downloaded from: http:///
maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. 12 __________________m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , sunnyva le , ca 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0 ? 1995 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. dg5 2 8 /dg5 2 9 8 -cha nne l la t c ha ble m ult iple x e rs maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. 12 __________________m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , sunnyva le , ca 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0 ? 1995 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. ___________________________________________pa c k a ge i nform a t ion (c ont inue d) c 0-15 a d b1 b dim a b b1 c e e1 e l l1 q s s1 min C 0.014 0.038 0.008 0.220 0.290 0.125 0.150 0.015 C 0.005 max 0.200 0.023 0.065 0.015 0.310 0.320 0.200 C 0.070 0.098 C min C 0.36 0.97 0.20 5.59 7.37 3.18 3.81 0.38 C 0.13 max 5.08 0.58 1.65 0.38 7.87 8.13 5.08 C 1.78 2.49 C 2.54 0.100 q l s1 e cerdip ceramic dual-in-line package (0.300 in.) s l1 e e1 pins 8 14 16 18 20 24 dim d d d d d d min C C C C C C max 0.405 0.785 0.840 0.960 1.060 1.280 min C C C C C C max 10.29 19.94 21.34 24.38 26.92 32.51 inches millimeters inches millimeters 21-0045a downloaded from: http:///

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